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Training in: Semiconductor memory device and chip design and modelling, device and chip processing, electrical characterization.
The > $100bn pa memory market is dominated by DRAM and flash. DRAM is fast with high endurance and low switching energy, but is also volatile and needs to be continually refreshed. In contrast, flash is non-volatile and cheap, but intrinsically slow and low endurance. Ideally, a memory should combine all the advantages of DRAM and flash, without any of the disadvantages, i.e. be fast with low switching energy, non-volatile, high endurance and low-cost; a so-called ‘universal memory’.
We are exploiting the extraordinary properties of III-Sb’s to develop a candidate universal memory technology that is expected to out-perform DRAM with the additional advantage of non-volatility. The memories uses the huge band offsets between InAs/AlSb in a triple-barrier resonant tunneling structure to solve the universal memory paradox of robust states that are easily changed.
The research will focus on the scaling of the technology from the current status of single bit devices and small arrays (4 and 64 bit) at the 20 micron node towards 1 Mbit arrays with scaled devices at <100 nm node. The researcher will model, design process and test (large arrays of) scaled single devices. Full facilities are available for device and circuit modelling, processing by photo- and e-beam lithography and electrical testing.
How to Apply
- An internal application form listing your academic and job records (.docx template available here).
- A free format CV (pdf format max 2 Mb)
- Official documentation such as degree and grades certificates will be required at a later stage.